Semiconductor technologies continuously evolve such that leading edge semiconductors have decreased geometries of transistor sizes and decreased voltages for voltage supplies. The smaller transistors are now manufactured with very thin gate oxide material. As a result, the dielectric breakdown voltage for such transistors in the leading edge semiconductor products has decreased. Thus, a decreased voltage supply is both desirable in order to reduce power consumption and necessary in order to avoid damaging the very thin gate oxide material. Meanwhile, other semiconductor products coupled to the leading edge semiconductor products still have much higher breakdown voltage devices, and utilize higher supply voltages.
For many years, semiconductor designers have dealt with the problem of translating between various levels of supply voltages. For example, when technology transferred between TTL (Transistor to Transistor Logic) to MOS (Metal Oxide Silicon) technology there was a need for voltage level shifting to be performed between the TTL and MOS technologies. Additionally, as supply voltages gradually decreased from 15 volts to 5 volts to 3 volts, designers created interface circuits which could operate between different voltage systems. However, most of those designs were focused on the issue of being able to just interface between one system operating at one voltage and a second system operating at a different voltage. Such systems typically did not have the problem of coping with breakdown voltages of transistors being threatened by the higher voltage system.
There are many chips and integrated circuits such as memories, memory controllers, and other peripherals that work with leading edge microprocessors. However, such peripherals and memories have not changed their supply voltages or reduced their voltage levels nearly as quickly as microprocessors have. In being able to interface between a peripheral circuit that has a much higher voltage than a leading edge integrated circuit, such as a microprocessor, designers often use a well biasing technique to try to minimize the impact in an integrated circuit of receiving a voltage signal much higher than the supply voltage intended for that integrated circuit. The well bias technique which is used eliminates a charge drain from the output node to an output stage power supply within the circuit. Prior circuits typically dealt with receiving higher voltage levels and using those voltage levels in a system operating at a lower voltage level. However, such systems did not typically worry about or have to compensate for transistor damage due to thin gate oxides. As technologies have evolved, the maximum voltage permitted across a transistor has decreased much faster than the decrease of supply voltages for the output bus. As a result, a need exists for a circuit and method which is able to guarantee the integrity of transistors and transistor gate oxides when interfacing with very high supply voltages at the output bus.
A known circuit for dealing with protecting gate oxides when coupling to an output bus having a higher supply voltage than the circuit supply voltage is illustrated in FIG. 1. An output buffer 10 has an input portion 11, an intermediate portion 12, and an output portion 13. In input portion 11, a P-channel transistor 15 has a source connected to a first (higher voltage) supply voltage V.sub.DDH, a gate connected to a node 24, and a drain connected to a node 17. A P-channel transistor 18 has a source connected to the supply voltage V.sub.DDH, and a gate connected a drain thereof at node 17. An N-channel transistor 20 has a drain connected to node 17, a gate connected to a second (lower voltage) supply voltage V.sub.DDL, and a source connected to a drain of an N-channel transistor 21. The gate of transistor 21 is connected to the DATA INPUT terminal, and a source of transistor 21 is connected to a ground terminal. Intermediate portion 12 includes an inverter 23 and an inverter 26 connected via a node 24 which is also connected to the gate of P-channel transistor 15. Inverters 23 and 26 are connected between the first supply voltage V.sub.DDH and the second supply voltage V.sub.DDL. The output portion 13 comprises P-channel transistors 28 and 29 and N-channel transistors 31 and 32. P-channel transistor 28 has a source connected to the first supply voltage V.sub.DDH, a gate connected to the output of inverter 26, and a drain connected to a source of transistor 29. P-channel transistor 29 has a gate connected to supply voltage V.sub.DDL, and a drain connected to a chip output terminal. N-channel transistor 31 has a drain connected to the chip output terminal, a gate connected to supply voltage V.sub.DDL, and a source connected to a drain of N-channel transistor 32. N-channel transistor 32 has a gate connected to the complement of the "DATA INPUT" signal, and has a source connected to the ground terminal.
In operation, circuit 10 is an output buffer with an input portion 11 which consumes DC power. Input portion 11 functions as a level shift stage. When the input data has a logic high level, node 17 is driven low by the input portion 11. However, node 17 does not assume a ground level potential, but rather node 17 is at a level which is driven below V.sub.DDL. Once node 17 is driven below V.sub.DDL, the first inverter 23 drives node 24 to the V.sub.DDH supply level. As a result, inverter 26 transitions the gate of transistor 28 to V.sub.DDL so that transistor 28 is made conductive. As a result, the chip output terminal is driven to the V.sub.DDH value. In the illustrated form, V.sub.DDL is a lower voltage magnitude than V.sub.DDH, and V.sub.DDH exceeds the maximum permitted voltage of the gate-to-source voltage, V.sub.GS, of each of the transistors of buffer 10. However, the difference between the V.sub.DDH voltage level and the V.sub.DDL voltage level is less than the maximum gate-to-source/drain voltage allowed in the technology in which buffer 10 is implemented.
When the DATA INPUT signal is at a logic low level, N-channel transistor 21 isolates node 17 from the ground terminal, and node 17 transitions to the V.sub.DDH potential. As a result, inverter 23 transitions node 24 to supply voltage V.sub.DDL and inverter 26 transitions the gate of transistor 28 to V.sub.DDH which makes transistor 28 non-conductive. Furthermore, transistor 32 is conductive and thus the chip output signal transitions to the ground terminal potential. Note in summary that output buffer 10 operates to consume power in the input portion 11 when the DATA INPUT signal is at logic high state. When the DATA INPUT signal is at a logic low state, power is not consumed. Although the power consumption of output buffer 10 is a potential problem for many applications, output buffer 10 functions to allow the circuit to interface with a system having a higher supply voltage. Additionally, output buffer 10 does not permit a voltage between the gate to source electrodes of each transistor which would destroy the gate oxide of that transistor.
Additionally output buffer 10 suffers from various limitations. If the two voltages are equal: V.sub.DDH =V.sub.DDL, output buffer 10 is not functional. The reason is that level shifted inverters do not work. It is common practice for a manufacturer of an Integrated Circuit to set voltage V.sub.DDH to V.sub.DDL during the debug phase of a design as well as for simplicity of test equipment during stress testing, such as is done in "bum-in" testing. Furthermore, the propagation delays of output buffer 10 do not track well as process technology, temperature, and voltage change, since transistors 28 and 32 are decoupled and are not driven from the same source. Part of this problem arises because the high and low output propagation paths differ significantly in circuit topology. Also note that output stage 13 tends to consume more active power than desired due to increased "crowbar" or short-circuit current due to different switching times through the two propagation paths since transistors 28 and 32 are decoupled.